1. Field of the Invention
The invention relates to a semiconductor device using a gate array, and also to a placing and wiring apparatus for placing and wiring logic elements so that a skew is not generated.
2. Description of the Related Art
Generally, a placing and wiring apparatus is employed to determine the placement of logic elements constituting the minimum unit of the placement and wiring, in a gate array having resistance and capacitance components, and then the layout of wirings for connecting the logic elements with each other.
FIG. 1 shows an example of circuits in which the placement and the layout of wirings have been conducted by such a placing and wiring apparatus. In the circuit shown in FIG. 1, 5 designates a logic element which outputs signals generated by the element itself, and logic elements 6, 7, 8 and 9 receive the signals from the logic element 5. The logic elements 5, 6, 7, 8 and 9 are interconnected by signal lines 23.
Each of the signal lines 23 constitutes a distributed constant circuit having a resistance component, capacitance component and a signal delay time which is uniquely determined by the resistance and the capacitance. When the resistance and/or the capacitance are increased, the signal delay time is lengthened. The resistance and capacitance of the signal line 23 which connects the logic element 5 with one of the logic elements 6, 7, 8 and 9 change in proportion to the length of the signal line, and therefore the signal delay time changes in accordance with the length of this signal line 23. When the signal lines 23 which respectively connect the logic element 5 with the logic elements 6, 7, 8 and 9 are different in length from each other, there occurs a phenomenon in which-the signals from the logic element 5 are inputted to the logic elements 6, 7, 8 and 9 after the elapse of different signal delay times (hereinafter, such a phenomenon is referred to as "skew"), causing inconvenience to the whole of the circuit incorporating these logic elements. In order to prevent a skew from occurring, therefore, there has been taken measures against a skew in which the lengths of the signal lines 23 respectively connecting the logic element 5 with the logic elements 6, 7, 8 and 9 are made equal to each other.
Hereinafter, the measures will be described in detail. It is assumed that the logic elements 5, 6, 7, 8 and 9 are positionally fixed. In order to equalize the distance between the logic element 5 and the logic element 6 to that between the logic element 5 and the logic element 7, the middle point 10 of the signal line 23 connecting the logic element 6 with the logic element 7 is determined to be a junction point at which the signal line 23 from the logic element 5 is connected to the signal line 23 connecting the logic element 6 with the logic element 7. In order to equalize the distance between the logic element 5 and the logic element 8 to that between the logic element 5 and the logic element 9, the middle point 11 of the signal line 23 connecting the logic element 8 with the logic element 9 is determined to be a junction point at which the signal line 23 from the logic element 5 is connected to the signal line 23 connecting the logic element 8 with the logic element 9.
Then, in order to equalize the distance between the logic element 5 and the logic element 6 (or 7) to that between the logic element 5 and the logic element 8 (or 9), a junction point 12 is determined at which the signal line 23 from the logic element 5 is connected to the signal line 23 connecting the middle points 10 and 11 with each other. A case where a circuit(s) exists in the gate array in which the placement of the logic elements and the wiring are to be conducted, before the placement of the logic elements will be considered (hereinafter, such a circuit(s) is referred to as "master data"). When the master data and a signal line other than the signal lines 23 are located in the vicinity of the junction point 12 and the junction point 12 is determined to be on the location of the master data or the other signal line, the signal lines connected at the junction point 12 cause the master data or the other signal line to become invalid. Therefore, such a location of the middle point is inadequate for a junction point.
To comply with this, the location of the junction point 12 is determined in a manner other than that described above, namely, in the following manner. While the location of the junction point 12 is fixed, a signal line 21 which has a length equal to the difference between the length from the logic element 5 to the logic element 8 (or 9) and that from logic element 5 to the logic element 6 (or 7) is inserted between the middle point, 10 and the junction point 12, so that the distance between the logic element 5 and the logic element 6 (or 7) becomes equal to that between the logic element 5 and the logic element 8 (or 9). When the signal line 21 is long, it is formed in a meandering form as shown in FIG. 1. The signal line 21 having such a shape is called a meandering wiring.
In FIG. 1, it is assumed that the middle points 10 and 1 can be moved which are determined so that the distances between the logic element 5 and the logic elements 6, 7, 8 and 9 are equal to each other. In some cases, also the middle points 10 and 11 cannot be moved for the same reason as that with respect to the junction point 12. In such cases, the signal lines connected to the middle points 10 and 11 are formed as meandering wirings.
FIG. 2 shows an example of circuits in which the placement and the layout of wirings have been conducted by a prior art placing and wiring apparatus so that a skew does not occur.
In the circuit shown in FIG. 2, the logic element 5 which outputs signals generated by the element itself is connected with a driver cell 13 and the meandering wiring 21 through the signal line 23 constituting the distributed constant circuit, and the driver cell 1.3 is connected with the logic elements 6, 7, 8 and 9 through the other signal lines 23. The meandering wiring 21 is connected with a driver cell 14 through another signal line 23, and the driver cell 14 is connected with logic elements 15, 16 and 17 through other signal lines 23. In the circuit, the logic element 5 must be connected with many logic elements. Accordingly, the driver cells 13 and 14 are disposed in order to drive the signals from the logic element 5 and transmit them to the logic elements 6, 7, 8, 9, 15, 16, 17 respectively.
Next, the measures for preventing a skew from occurring in the circuit of FIG. 2 will be described.
It is assumed that the placement of the logic elements 6, 7, 8, 9, 15, 16, 17 and that of the signal lines 23 are previously determined. In order that signals from the logic element 5 should be inputted to the logic elements 6 and 7 after the elapse of the same signal delay time, the middle point 10 of the signal line 23 connecting the logic elements 6 and 7 with each other is determined to be a junction point at which the signal line 23 from the logic element 5 is connected with the signal line 23 connecting the logic elements 6 and 7 with each other, so as to make the distance between the logic elements 5 and 6 equal to that between the logic elements 5 and 7. Then, in order that signals from the logic element 5 should be inputted to the logic elements 8 and 9 after the elapse of the same signal delay time, the middle point 11 of the signal line 23 connecting the logic elements 8 and 9 with each other is determined to be a junction point at which the signal line 23 from the logic element 5 is connected with the signal line 23 connecting the logic elements 8 and 9 with each other, so as to make the distance between the logic elements 5 and 8 equal to that between the logic elements 5 and 9.
A junction point 12 at which the signal line 23 from the logic element 5 is connected with the signal line 23 connecting the logic elements 6 (or 7) and 8 (or 9) with each other is determined so that signals from the logic element 5 are inputted to the logic elements 6 (or 7) and 8 (or 9) after the elapse of the same signal delay time, thereby making the distance between the logic elements 5 and 6 (or 7) equal to that between the logic elements 5 and 8 (or 9). In order that signals from the logic element 5 are inputted to the logic elements 15 and 16 after the elapse of the same signal delay time, the middle point 18 of the signal line 23 connecting the logic elements 15 and 16 is determined to be a junction point at which the signal line 23 from the logic element 5 is connected with the signal line 23 connecting the logic elements 15 and 16 with each other, so as to make the distance between the logic elements 5 and 15 equal to that between the logic elements 5 and 16.
A junction point 19 at which the signal line 23 from the logic element 5 is connected with the signal line 23 connecting the logic elements 15 (or 16) and 17 with each other is determined so that signals from the logic element 5 are inputted to the logic elements 15 (or 16) and 17 after the elapse of the same signal delay time, thereby making the distance between the logic elements 5 and 15 (or 16) equal to that between the logic elements 5 and 17. Then, a junction point 20 at which the signal line 23 from the logic element 5 is connected with the signal line 23 connecting the logic elements 6, 7, 8 and 9 with the logic elements 15, 16 and 17 is determined so that the signal delay time of the signal transmission from the logic element 5 to the logic elements 6, 7, 8 and 9 is equal to that of the signal transmission from the logic element 5 to the logic elements 15, 16 and 17. When a master data or another signal line is located in the vicinity of the junction point 20 and the junction point 20 cannot be moved the meandering wiring which has a length corresponding to the required difference in wiring length must be inserted between the junction point 20 and the driver cell 14 so as to make the signal delay time of the signal transmission from the logic element 5 to the logic elements 6, 7, 8 and 9 equal to that of the signal transmission From the logic element 5 to the logic elements 15, 16 and 17.
On the other hand, the signal delay times of the driver cells 13 and 14 are different from each other depending on their respective fan out. In order to determine the length of the meandering wiring 21, accordingly, it is necessary to consider the lengths of the signal lines 23 connecting the logic element 5 with the logic elements 6, 7, 8 and 9, the lengths of the signal lines 23 connecting the logic element 5 with the logic elements 15, 16 and 17, and the difference between the signal delay time of the driver cell 13 and that of the driver cell 14.
Since the difference in signal delay time between the driver cells 13 and 14 is short, the signal delay time cannot be adjusted by using the driver cells 13 and 14.
As described above, the meandering wiring 21 is used in a prior art placing and wiring apparatus. When the meandering wiring 21 is long, a wide region is assigned to the meandering wiring. This prohibits transistors existing in the meandering wiring region from being used as logic elements, thereby producing a problem in that the ratio of the number of available logic elements to the number of all transistors is lowered (hereinafter, the ratio is referred to as "gate available ratio").